Method and apparatus for measuring device mismatches
US7408372B2 · kind B2 · utility
10Cited by
3References
6Claims
0Family size
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Key dates
| Filing date | Jun 8, 2006 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Jan 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.