Method and apparatus for a redundant transceiver architecture
US7408380B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2006 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Aug 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17764
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus to provide various mechanisms to improve yield of an integrated circuit (IC) employing serial input/output (I/O) communication devices. A single error correction model provides one spare transceiver per group of primary transceivers, whereby reconfiguration of the IC isolates the defective transceiver and configures the replacement transceiver for operation in its place. A multiple error correction model is also provided, whereby multiple replacement transceivers may be configured to replace multiple defective transceivers. The replacement mechanism may occur during various phases of the IC, such as during wafer testing, final testing, or post-deployment testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.