Method, apparatus and system sharing an operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry
US7408496B2 · kind B2 · utility
4Cited by
10References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 21, 2006 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Aug 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/442
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry. The operational amplifier contains two input circuits that are time multiplexed in a manner that allows capacitance to be discharged at one input circuit while the other input circuit is inputting signals into the amplifier. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.