Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response
US7409504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2005 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Apr 30, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for sequentially coupling successive processor requests for a cache line before the data is received in the cache of a first coupled processor. Both homogenous and non-homogenous operations are chained to each other, and the coherency protocol includes several new intermediate coherency responses associated with the chained states. Chained coherency states are assigned to track the chain of processor requests and the grant of access permission prior to receipt of the data at the first processor. The chained coherency states also identify the address of the receiving processor. When data is received at the cache of the first processor within the chain, the processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chained coherency protocol frees up address bus bandwidth by reducing the number of retries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.