System and method for responding to TLB misses
US7409524B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2005 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Apr 16, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.