Error-detection flip-flop
US7409631B2 · kind B2 · utility
14Cited by
9References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2005 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Jun 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31726
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input signal is received during a predetermined clock period, signifying a timing error. The error-detection flip-flop produces a variable-length error pulse, which may be combined with other error pulses and converted to a stable signal for sampling by error-correction circuitry. The error-detection flip-flop does not increase the clocking power of the digital circuit and consumes little additional circuit area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.