3D integrated circuits using thick metal for backside connections and offset bumps
US7410884B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2005 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Feb 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Backside connections for 3D integrated circuits and methods to fabricate thereof are described. A stack of a first wafer over a second wafer that has a substrate of the first wafer on top of the stack, is formed. The substrate of the first wafer is thinned. A first dielectric layer is deposited on the thinned substrate. First vias extending through the substrate to the first wafer are formed in the first dielectric layer. A conductive layer is deposited in the first vias and on the first dielectric layer to form thick conductive lines. Second dielectric layer is formed on the conductive layer. Second vias extending to the conductive lines are formed in the second dielectric layer. Conductive bumps extending into the second vias and offsetting the first vias are formed on the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.