Post last wiring level inductor using patterned plate process
US7410894B2 · kind B2 · utility
4Cited by
12References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2005 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Aug 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.