Kunal Vaed
23Patents
8h-index
23Co-inventors
71Inventor score
Filing activity: Dec 13, 2002 → Jan 27, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7662722B2 | Air gap under on-chip passive device | Electricity | 22 | Active |
| US7005371B2 | Method of forming suspended transmission line structures in back end of line processing | Electricity | 14 | Expired |
| US6992344B2 | Damascene integration scheme for developing metal-insulator-metal capacitors | Electricity | 13 | Expired |
| US7361950B2 | Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric | Electricity | 12 | Expired |
| US7622357B2 | Semiconductor device structures with backside contacts for improved heat dissipation and reduced parasitic resistance | Electricity | 12 | Active |
| US7545007B2 | MOS varactor with segmented gate doping | Electricity | 12 | Expired |
| US7608909B2 | Suspended transmission line structures in back end of line processing | Electricity | 10 | Active |
| US7439151B2 | Method and structure for integrating MIM capacitors within dual damascene processing techniques | Electricity | 9 | Active |
| US6940117B2 | Prevention of Ta2O5 mim cap shorting in the beol anneal cycles | Electricity | 7 | Expired |
| US7741698B2 | Post last wiring level inductor using patterned plate process | Electricity | 6 | Active |
| US7573117B2 | Post last wiring level inductor using patterned plate process | Electricity | 6 | Active |
| US7394145B2 | Methods of fabricating passive element without planarizing and related semiconductor device | Electricity | 6 | Active |
| US7915134B2 | Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material | Electricity | 5 | Active |
| US7763954B2 | Post last wiring level inductor using patterned plate process | Electricity | 5 | Active |
| US7410894B2 | Post last wiring level inductor using patterned plate process | Electricity | 4 | Active |
| US7910450B2 | Method of fabricating a precision buried resistor | Electricity | 3 | Active |
| US7691717B2 | Polysilicon containing resistor with enhanced sheet resistance precision and method for fabrication thereof | Electricity | 3 | Active |
| US7427550B2 | Methods of fabricating passive element without planarizing | Electricity | 3 | Active |
| US7732294B2 | Post last wiring level inductor using patterned plate process | Electricity | 1 | Active |
| US8119491B2 | Methods of fabricating passive element without planarizing and related semiconductor device | Electricity | 1 | Active |
| US8487401B2 | Methods of fabricating passive element without planarizing and related semiconductor device | Electricity | 0 | Active |
| US7354872B2 | Hi-K dielectric layer deposition methods | Electricity | 0 | Active |
| US7732295B2 | Post last wiring level inductor using patterned plate process | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.