Driver circuit with reduced jitter between circuit domains

US7411439B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Martin Brox · Munich, DE
• Maksim Kuzmenka · Birkenfeld, DE

Key dates

• Filing date: Oct 27, 2005
• Grant date: Aug 12, 2008
• Expiry date: Jan 4, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/018521
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A circuit for coupling a logic signal from a circuit input to a circuit output includes a parallel connection of a first circuit branch and a second circuit branch, wherein an inverter in the first branch powered as last inverter in this branch via first supply terminals, via which a first supply potential and a second supply potential are supplied, and an inverter in the second branch powered as first inverter in this branch via second supply voltage terminals, via which a second supply potential and a second reference potential are supplied, are adapted to receive the same logic value of the logic signal, wherein outputs of the two circuit branches are connected to each other and coupled to the circuit output. In such a circuit, propagation time differences of rising and falling edges, which may develop by fluctuation of various supply potentials, may be minimized. Thus, a transition from an internal supply potential to an external supply potential may take place, without noticeably degrading the signal timing.