Power amplifying semiconductor integrated circuit device for use in communication equipment
US7411457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2006 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Sep 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/387
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is to provide a technique which optimizes a gate resistor of a bias circuit to thereby make it possible to greatly improve a distortion characteristic of a power amplifier. A bias circuit used as for biasing the gate of a final-stage power transistor is included in a power amplifier provided in a communication mobile system. In the bias circuit, an inductance and a resistor are series-connected between a power supply voltage and the gate of the power transistor. The resistance value of the resistor is set to approximately the same order as an input impedance of the power transistor. When the input impedance of the power transistor is about 10Ω or so, for example, the resistor is set to about a few Ω to about 100Ω. Thus, the gain of the power transistor at a low-frequency band can greatly be suppressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.