Sense mechanism for microprocessor bus inversion
US7411840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2004 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Dec 2, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense mechanism for data bus inversion including a first memory device and an analog adder. The first memory device stores bits of the bus in a previous bus cycle. The analog adder compares the bits of the bus in the previous bus cycle with bits of the bus in a current bus cycle and provides a data inversion signal indicative of whether more than half of the bits of the bus have changed state. The analog adder operates as a bus state change sense device which rapidly evaluates bus state changes from one bus cycle to the next. The data inversion signal is used for selectively inverting the data bits of the bus and indicating bus inversion according to data bus inversion operation, such as according to X86 microprocessor protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.