Semiconductor device
US7411851B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 18, 2006 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Jul 28, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fuse peripheral circuit shown in FIG. 2 has a fuse 10, a potential difference imparting circuit 20, a potential difference reducing circuit 30, a terminal 40, a memory circuit 50, a transfer gate 60, and a logic gate 70. The potential difference imparting circuit 20 is configured as having a transfer gate 22 (first transfer gate), a terminal 24 (first terminal) and a terminal 26, so as to give a predetermined potential difference between both ends of the fuse 10 when disconnection of the fuse 10 is judged. The potential difference reducing circuit 30 is configured as having a transfer gate 32 (second transfer gate), a terminal 34 (second terminal) and a terminal 36, and reduces the potential difference between both ends of the fuse 10 applied by the above-described potential difference imparting circuit 20.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.