Patent · US Active

Optoelectronic alignment structures for the wafer level testing of optical and optoelectronic chips

US7412138B1 · kind B1 · utility

8Cited by

3References

5Claims

0Family size

Assignee

Luxtera, Inc. · US

Inventors

Roman Malendevich · Oceanside, US
Myles Sussman · San Mateo, US
Lawrence C. Gunn, III · Encinitas, US

Key dates

Filing date	Feb 28, 2007
Grant date	Aug 12, 2008
Priority date	—
Expiry date	Apr 28, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG02B6/4224
WIPO fieldOptics
WIPO sectorInstruments

Abstract

This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light to/from the top of a wafer. A wafer level test system uses optical and electronic probes to search for and align with an optoelectronic alignment structure. The test system uses a located optoelectronic alignment structure as a reference point to locate other devices on the wafer. The system tests the operation of selected devices disposed on the wafer. The optoelectronic alignment loop is also used as an alignment reference of known performance for an adjacent device of unknown performance.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.