Self-synchronizing pseudorandom bit sequence checker
US7412640B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2003 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Jun 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/242
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.