Semiconductor device with improved overlay margin and method of manufacturing the same
US7414279B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 2, 2005 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Aug 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.