Device and method for the synchronization of clock signals and adjustment of the duty cycle of the clock signal
US7414445B2 · kind B2 · utility
25Cited by
4References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 2, 2006 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Sep 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device for synchronizing an input clock signal with an output clock signal is disclosed. One embodiment includes includes a bistable trigger circuit for controlling the edges of a clock signal fed to a first delay, a second phase comparator for determining the phase between the first clock signal delayed by the first delay and the input clock signal, and a second controller for controlling the delay of the first clock signal in correspondence with the phase determined by the second phase comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.