Erase verify method for NAND-type flash memories
US7414891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2007 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Feb 5, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value used in read mode and by biasing the all even word lines at the pass voltage value used in read mode of the selected unit. Verifying the odd and even word lines may be performed in either order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.