Patent · US Expired

Memory component having a novel arrangement of the bit lines

US7414906B2 · kind B2 · utility

0Cited by

5References

4Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Florian Schnabel · Ehrenkirchen, DE
Helmut Schneider · Hersbruck, DE

Key dates

Filing date	Dec 12, 2005
Grant date	Aug 19, 2008
Priority date	—
Expiry date	Jan 19, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH10D89/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory component comprises a plurality of bit lines, on which memory cells are arranged, and a plurality of sense amplifiers, which are arranged in a row, each sense amplifier being connected to two bit lines. A bit line which is connected to a first sense amplifier in the row is arranged directly adjacent to a bit line which is connected to a second sense amplifier in the same row.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.