MOS transistor forming method
US7416950B2 · kind B2 · utility
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50Claims
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Key dates
| Filing date | Feb 9, 2006 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | May 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming, in a single-crystal semiconductor substrate of a first conductivity type, doped surface regions of the second conductivity type and deeper doped regions of the first conductivity type underlying the surface regions, including the step of negatively biasing the substrate placed in the vicinity of a plasma including, in the form of cations dopants of the first conductivity type and dopants of a second conductivity type, the dopants of the second conductivity type having an atomic mass which is greater than that of the dopants of the first conductivity type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.