Semiconductor device and method of manufacturing the same
US7417284B2 · kind B2 · utility
7Cited by
10References
3Claims
0Family size
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Key dates
| Filing date | Dec 13, 2005 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Dec 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/252
Abstract
A semiconductor device having SJ structure has a peripheral region having a higher withstand voltage than the withstand voltage of the cell region. A semiconductor upper layer including second conductivity-type impurities and a semiconductor lower layer including first conductivity-type impurities whose concentration is lower than the first portion region constituting the combination of the cell region are formed in the semiconductor layer of the peripheral region. A field oxide layer is formed on a surface of the semiconductor upper layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.