Adaptive gate voltage regulation
US7417904B2 · kind B2 · utility
31Cited by
19References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2006 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Dec 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.