Versatile register file design for a multi-threaded processor utilizing different modes and register windows
US7418582B1 · kind B1 · utility
62Cited by
56References
24Claims
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Key dates
| Filing date | May 13, 2004 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Jan 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimizing a register file hierarchy in a multithreaded processor. The method includes providing a register file hierarchy with a plurality of register file cells, associating the plurality of register file cells with respective threads when the processor is operating in a multithreaded mode and flattening the plurality of register file cells with a single thread when the processor is operating in a single threaded mode. The register file cells correspond to threads of the multithreaded processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.