System and method for reducing the power consumption of clock systems
US7418675B2 · kind B2 · utility
4Cited by
4References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2006 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | May 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells are a subset of previously placed cells of the integrated circuit. The placement of synchronous cells is performed to reduce a current needed from the clock driver to drive the plurality of synchronous cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.