Layout method for miniaturized memory array area
US7418685B2 · kind B2 · utility
0Cited by
5References
16Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jun 25, 2004 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Sep 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bit lines and a pair of two tungsten wires having the same widths are formed at a portion where a through-hole is to be formed such that the bit lines and the tungsten wires are arranged at regular intervals. A through-hole for connection to another wiring layer is formed between the tungsten wires. A connection wiring made of tungsten is formed over the through-hole so as to have a predetermined margin around the through-hole. In a photolithography process, a slit having a small width enough to be insensitive to a photo-resist is formed so as to span the through-hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.