Method for forming stacked via-holes in a multilayer printed circuit board
US7418780B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2006 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Dec 12, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An exemplary method for forming stacked via-holes in a multilayer printed circuit board includes the steps of: providing a base circuit board; attaching a first copper-coated-substrate having a first substrate and a first copper layer thereon and a second copper-coated-substrate having a second substrate and a second copper layer thereon onto the base circuit board in a manner such that; forming at least one first window in the second copper layer, making at least one first hole in the second substrate through the at least one first window, forming at least one second window in the first copper layer through the at least one first hole, and making at least one second hole in the first substrate through the at least one second window, thus forming at least one part-finished stacked via-hole; and plating the at least one part-finished stacked via-hole thereby forming at least one stacked via-hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.