Method of fabrication for chip scale package for a micro component
US7419853B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2005 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Mar 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A package includes a sensor die with a micro component, such as a MEMS device, coupled to an integrated circuit which may include, for example, CMOS circuitry, and one or more electrically conductive bond pads near the periphery of the sensor die. A semiconductor cap structure is attached to the sensor die. The front side of the cap structure is attached to the sensor die by a seal ring to hermetically encapsulate an area of the sensor die where the micro component is located. The bond pads on the sensor die are located outside the area encapsulated by the seal ring. Electrical leads, which extend along outer side edges of the semiconductor cap structure from its front side to its back side, are coupled to the micro component via the bond pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.