Recessed-gate thin-film transistor with self-aligned lightly doped drain

US7419858B2 · kind B2 · utility

Assignee

• Sharp Laboratories of America, Inc. · US

Inventors

• Paul J. Schuele · Washougal, US
• Mark Albert Crowder · Portland, US
• Apostolos T. Voutsas · Vancouver, US
• Hidayat Kisdarjono · Vancouver, US

Key dates

• Filing date: Aug 31, 2006
• Grant date: Sep 2, 2008
• Expiry date: Nov 14, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/027

Abstract

A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.