Power LDMOS transistor
US7420247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2005 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Aug 9, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
Abstract
A LDMOS transistor comprises a trench formed through the epitaxial layer at least to the top surface of the substrate, the trench having a bottom surface and a sidewall contacting the source region and the portion of the channel region extending under the source region. A first insulating layer is formed over the upper surface and sidewall surfaces of the conductive gate. A continuous layer of conductive material forming a source contact and a gate shield electrode is formed along the bottom surface and the sidewall of the trench and over the first insulating layer to cover the top and sidewall surfaces of the conductive gate. A second insulating layer is formed over an active area of the transistor, including over the continuous layer of conductive material and filling the trench. A drain electrode can extend over the second insulating layer to substantially cover the active area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.