Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design size
US7420390B1 · kind B1 · utility
49Cited by
6References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2006 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Jan 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A field programmable gate array includes a plurality of programmable logic blocks to implement one or more logic functions. The field programmable gate array includes a plurality of independent registers not associated with any specific one of the plurality of programmable logic blocks. The plurality of independent registers may be programmed to support any one of the plurality of programmable logic blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.