Frequency modulated output clock from a digital phase locked loop
US7420426B2 · kind B2 · utility
5Cited by
5References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 30, 2005 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Mar 18, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency modulated output of a digital locked loop (DLL) is implemented with a Johnson Counter outputting a sample clock and a synchronized digital code at a multiple of the sample clock. The digital code drives a digital-to-analog converter to generate a frequency modulated control signal. The control signal is summed with the center frequency control from the digital locked loop digital filter to provide a frequency modulated center frequency control signal to the DLL oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.