Method for extracting and modeling semiconductor device series resistance and for simulating a semiconductor device with use thereof
US7421383B2 · kind B2 · utility
2Cited by
2References
23Claims
0Family size
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Key dates
| Filing date | Jan 15, 2003 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Nov 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor device junction simulation is carried out utilizing models that are developed with series resistance extractions that improve their fidelity particularly in the high current regions of device operation. The models may also be tailored to account for geometric considerations of the semiconductor devices thereby allowing for a more flexible model and simulation by providing for geometric scaling capabilities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.