Annotating timing information for a circuit design for increased timing accuracy
US7421675B1 · kind B1 · utility
3Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2006 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Apr 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of annotating timing information for a circuit design for performing timing analysis can include determining minimum and maximum clock path delays for registers of a circuit design and computing a difference between the maximum clock path delay and the minimum clock path delay for a destination register of the circuit design. The method further can include adjusting a register timing parameter for the destination register according to the difference and performing a timing verification on the destination register using the adjusted register timing parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.