Strained silicon MOS device with box layer between the source and drain regions

US7422950B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Giuseppe Curello · Portland, US
• Hemant Deshpande · Beaverton, US
• Sunit Tyagi · Portland, US
• Mark Bohr · Beaverton, US

Key dates

• Filing date: Dec 14, 2005
• Grant date: Sep 9, 2008
• Expiry date: Jul 19, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822

Abstract

A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.