Patent · US Expired

Two-level interrupt service routine

US7424563B2 · kind B2 · utility

1Cited by

12References

24Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Michael Egnoah Birenbach · Cary, US
Gregory Brookshire · Cary, US
James Norris Dieffenderfer · Apex, US
Stephen G. Geist · Raleigh, US
Richard A. Moore · Newport, US
Thomas Andrew Sartorius · Raleigh, US
Rodney Wayne Smith · Raleigh, US

Key dates

Filing date	Feb 24, 2006
Grant date	Sep 9, 2008
Priority date	—
Expiry date	May 11, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/4812
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processor provides two-level interrupt servicing. In one embodiment, the processor comprises a storage device and an interrupt handler. The storage device is configured to store an interrupt identifier corresponding to an interrupt request. The interrupt handler is configured to recognize the interrupt request, initiate a common interrupt service routine responsive to recognizing the interrupt request and subsequently initiate an interrupt service routine corresponding to the stored interrupt identifier.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.