Rodney Wayne Smith
71Patents
9h-index
52Co-inventors
81Inventor score
Filing activity: Feb 25, 1976 → Nov 9, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7716460B2 | Effective use of a BHT in processor having variable length instruction set execution modes | Physics | 48 | Active |
| US10108417B2 | Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor | Physics | 40 | Active |
| US7624256B2 | System and method wherein conditional instructions unconditionally provide output | Physics | 20 | Expired |
| US7624254B2 | Segmented pipeline flushing for mispredicted branches | Physics | 16 | Active |
| US8438372B2 | Link stack repair of erroneous speculative update | Physics | 15 | Active |
| US6513134B1 | System and method for tracing program execution within a superscalar processor | Physics | 14 | Expired |
| US7278012B2 | Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions | Physics | 13 | Expired |
| US7971044B2 | Link stack repair of erroneous speculative update | Physics | 10 | Active |
| US7415638B2 | Pre-decode error handling via branch correction | Physics | 10 | Active |
| US4003275A | Wrench | Performing Operations; Transporting | 9 | Expired |
| US7587580B2 | Power efficient instruction prefetch mechanism | Physics | 8 | Expired |
| US7676659B2 | System, method and software to preload instructions from a variable-length instruction set with proper pre-decoding | Physics | 8 | Active |
| US7805588B2 | Caching memory attribute indicators with cached memory data field | Emerging Cross-Sectional Technologies | 7 | Active |
| US7366877B2 | Speculative instruction issue in a simultaneously multithreaded processor | Physics | 7 | Expired |
| US7421568B2 | Power saving methods and apparatus to selectively enable cache bits based on known processor state | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6948053B2 | Efficiently calculating a branch target address | Physics | 5 | Expired |
| US6816962B2 | Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions | Physics | 5 | Expired |
| US7711927B2 | System, method and software to preload instructions from an instruction set other than one currently executing | Physics | 5 | Active |
| US7669039B2 | Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instruction | Physics | 4 | Active |
| US7802055B2 | Virtually-tagged instruction cache with physically-tagged behavior | Physics | 4 | Active |
| US7984279B2 | System and method for using a working global history register | Physics | 4 | Active |
| US7406613B2 | Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions | Emerging Cross-Sectional Technologies | 4 | Expired |
| US7404042B2 | Handling cache miss in an instruction crossing a cache line boundary | Physics | 4 | Active |
| US7827392B2 | Sliding-window, block-based branch target address cache | Physics | 3 | Active |
| US8943300B2 | Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information | Physics | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.