Interconnect integrity verification
US7424690B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2004 |
| Grant date | Sep 9, 2008 |
| Priority date | — |
| Expiry date | Apr 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for designing a complex electronic circuit by simulating blocks of the circuit using various simulators to produce a net list, designing the physical layout of the circuit using a layout tool that produces a layout verses schematic reference file, mapping the reference file to the net list to create a mapping file, and analyzing the mapping file to verify that the layout meets various criteria. Each block may be verified using simulation tools that are appropriate for that piece of the overall circuit, and using conditions that may maximize the strain on the circuit. The results from the simulations are compared to the physical layout to determine if the physical layout is able to properly conduct the electrical signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.