Assigning inputs of look-up tables to improve a design implementation in a programmable logic device
US7424697B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2007 |
| Grant date | Sep 9, 2008 |
| Priority date | — |
| Expiry date | May 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for improving an implementation of a design in a programmable logic device (PLD). A topological level of the design implementation is determined for each look-up table (LUT) of the PLD. A subset of the LUTs that are on the critical timing paths of the design implementation is determined. For each LUT in the subset at each topological level, a set combinations is determined for assigning signals to the inputs of the LUT. A current assignment of the signals to the LUT inputs is initialized according to the design implementation. For each LUT in the subset at each topological level, the method determines whether a respective assignment for each combination in the set for the LUT improves a timing metric for the LUT relative to the current assignment for the LUT, and the current assignment is updated when the respective assignment improves the timing metric for the LUT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.