Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors

US7425488B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• Hanming Wu · Shanghai, CN
• Jiang Zhang · Shanghai, CN
• John Chen · Palo Alto, US
• Xian J. Ning · Potsdam, US

Key dates

• Filing date: Oct 5, 2005
• Grant date: Sep 16, 2008
• Expiry date: Oct 5, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material (e.g., silicon/germanium, silicon carbide) in an etched source region and an etched drain region. Preferably, the etched source region and the etched drain region are coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the fill material formed in the etched source region and the etched drain region.