Programmable logic device multi-boot state machine for serial peripheral interface (SPI) programmable read only memory (PROM)
US7425843B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2007 |
| Grant date | Sep 16, 2008 |
| Priority date | — |
| Expiry date | Aug 7, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17758
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Multiple configurations are provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA), when connected to a serial peripheral interface programmable read only memory (SPI PROM) by using a programmable SPI address register incorporated into a SPI state machine of the PLD. A read command followed by a first address corresponding to first configuration data is sent from the SPI address register of the SPI state machine of the PLD to the SPI PROM. Data starting at the first address in the SPI PROM is then read by the PLD from the SPI PROM along with a second address corresponding to second configuration data. The first configuration data is stored in the PLD memory, and the second address is stored in the SPI address register. These steps may be repeated for subsequent boots of the PLD for additional configurations of the PLD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.