Programmable memory device circuit
US7426131B2 · kind B2 · utility
16Cited by
2References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 1, 2006 |
| Grant date | Sep 16, 2008 |
| Priority date | — |
| Expiry date | Nov 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5631
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits for writing, reading, and erasing a programmable metallization cell are disclosed. The programming circuits compensate for parasitic capacitance and/or parasitic resistance. The parasitic resistance and/or capacitance is compensated for using a feedback loop or a time current filter. Various circuits also measure a switching speed of the programmable metallization cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.