Combined hardware/software assertion checking
US7426705B1 · kind B1 · utility
22Cited by
0References
14Claims
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Assignee
Inventor
Key dates
| Filing date | May 2, 2005 |
| Grant date | Sep 16, 2008 |
| Priority date | — |
| Expiry date | Aug 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Assertion checking is achieved by modifying a given set of assertions to include subsuming assertions that cover one or more of given assertions and also require less logic to implement, by implementing at least the subsuming assertions in functionally reconfigurable circuitry within an integrated circuit, and by checking with an auxiliary tester assertions that each of the firing subsuming assertion replaced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.