Multi bridge channel field effect transistors with nano-wire channels and methods of manufacturing the same
US7427788B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2005 |
| Grant date | Sep 23, 2008 |
| Priority date | — |
| Expiry date | Jan 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A field effect transistor (FET) includes spaced apart source and drain regions disposed on a substrate and at least one pair of elongate channel regions disposed on the substrate and extending in parallel between the source and drain regions. A gate insulating region surrounds the at least one pair of elongate channel regions, and a gate electrode surrounds the gate insulating region and the at least one pair of elongate channel regions. Support patterns may be interposed between the semiconductor substrate and the source and drain regions. The elongate channel regions may have sufficiently small cross-section to enable complete depletion thereof. For example, a width and a thickness of the elongate channel regions may be in a range from about 10 nanometers to about 20 nanometers. The elongate channel regions may have rounded cross-sections, e.g., each of the elongate channel regions may have an elliptical cross-section. The at least one pair of elongate channel regions may include a plurality of stacked pairs of elongate channel regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.