Drain-extended MOS transistors and methods for making the same
US7427795B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Sep 23, 2008 |
| Priority date | — |
| Expiry date | Jun 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon layer (106). The p-buried layer (130) may be formed above an n-buried layer (120) in the substrate (104) for high-side driver transistor (T2) applications, wherein the p-buried layer (130) extends between the drain-extended MOS transistor (T2) and the n-buried layer (120) to inhibit off-state breakdown between the source (154) and drain (156).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.