Method and system for execution and latching of data in alternate threads
US7428653B2 · kind B2 · utility
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3References
7Claims
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Key dates
| Filing date | Jul 20, 2005 |
| Grant date | Sep 23, 2008 |
| Priority date | — |
| Expiry date | Dec 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An alternate multi-thread pipeline structure and method are provided. A deep pipeline is provided in which two threads of two separate pipeline stages are alternatively presented to the various logic and latch circuits for execution. The execution and latching of the threads alternates from one thread to the other within a single clock cycle. Thus, each thread is executed once per clock cycle and two threads are executed in a single clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.