Enhanced incremental placement during physical synthesis
US7428718B1 · kind B1 · utility
6Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2006 |
| Grant date | Sep 23, 2008 |
| Priority date | — |
| Expiry date | Nov 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of placing a circuit design for a target device can include identifying a critical region having at least one input block and at least one output block and determining a line starting at the input block and extending to the output block. Blocks of the critical region can be assigned to sites located on, or proximate to, the line according to connectivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.