Semiconductor device with a gate electrode having a laminate structure
US7429777B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2006 |
| Grant date | Sep 30, 2008 |
| Priority date | — |
| Expiry date | Feb 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.