Method and apparatus for controlling a processor in a data processing system
US7430658B2 · kind B2 · utility
1Cited by
4References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 13, 2007 |
| Grant date | Sep 30, 2008 |
| Priority date | — |
| Expiry date | Jun 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for controlling a processor in a data processing system is described. In an example, the processor is maintained in a halt condition in response to reset information received from the data processing system (e.g., initialization of an integrated circuit having a processor embedded therein). At least one memory resource in communication with the processor is configured. The processor is then released from the halt condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.