Semiconductor package and fabrication process thereof
US7432601B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 10, 2006 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Oct 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package mainly includes a chip, a substrate, an encapsulant, a plurality of external terminals and a stress release layer. The substrate has an upper surface and a lower surface. The chip is disposed on the upper surface of the substrate by a chip-attached layer and electrically connected to the substrate. The encapsulant is formed above the upper surface of the substrate. The external terminals are disposed on the lower surface of the substrate. The stress release layer is formed on the interface of the substrate and the encapsulant such that the external terminals are movable with respect to the encapsulated chip. In addition, a fabrication process of the semiconductor package is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.