Patent assignee · TW · COMPANY

Powertech Technology Inc.

196Patents
196Active
196Granted
58Portfolio score

Filing activity: Sep 1, 2006 → Nov 30, 2022 · 53 expiring within 5 years

Most-cited patents

PatentTitleAreaCited byStatus
US7569935B1 Pillar-to-pillar flip-chip assembly Emerging Cross-Sectional Technologies 101 Active
US10157828B2 Chip package structure with conductive pillar and a manufacturing method thereof Electricity 49 Active
US7902666B1 Flip chip device having soldered metal posts by surface mounting Electricity 29 Active
US7619305B2 Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking Emerging Cross-Sectional Technologies 22 Active
US7838967B2 Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips Electricity 21 Active
US7776649B1 Method for fabricating wafer level chip scale packages Electricity 19 Active
US8420437B1 Method for forming an EMI shielding layer on all surfaces of a semiconductor package Electricity 18 Active
US7633143B1 Semiconductor package having plural chips side by side arranged on a leadframe Electricity 16 Active
US8703508B2 Method for wafer-level testing diced multi-chip stacked packages Electricity 14 Active
US8368192B1 Multi-chip memory package with a small substrate Electricity 11 Active
US9716080B1 Thin fan-out multi-chip stacked package structure and manufacturing method thereof Electricity 10 Active
US10128211B2 Thin fan-out multi-chip stacked package structure and manufacturing method thereof Electricity 10 Active
US8115319B2 Flip chip package maintaining alignment during soldering Electricity 10 Active
US8237273B2 Metal post chip connecting device and method free to use soldering material Electricity 10 Active
US9761568B2 Thin fan-out multi-chip stacked packages and the method for manufacturing the same Electricity 9 Active
US7884472B2 Semiconductor package having substrate ID code and its fabricating method Electricity 9 Active
US7927919B1 Semiconductor packaging method to save interposer Electricity 8 Active
US8710859B2 Method for testing multi-chip stacked packages Physics 8 Active
US9842811B1 Heat-dissipating semiconductor package for lessening package warpage Electricity 8 Active
US9099364B1 MPS-C2 semiconductor device having shorter supporting posts Electricity 8 Active
US9887148B1 Fan-out semiconductor package structure and fabricating method Electricity 7 Active
US7408245B2 IC package encapsulating a chip under asymmetric single-side leads Electricity 7 Active
US9627228B1 Method for manufacturing a chip package having a coating layer Electricity 7 Active
US9419033B2 Chip scale package of image sensor having dam combination Electricity 7 Active
US7902663B2 Semiconductor package having stepwise depression in substrate Electricity 6 Active

Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.